1. Field of the Invention
The present invention is related to a high-voltage selecting circuit, and more particularly, to a high-voltage selecting circuit without a voltage drop.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional high-voltage selecting circuit 100. The high-voltage selecting circuit 100 includes selecting P-channel Metal Oxide Semiconductor (PMOS) transistors QPS1 and QPS2. The selecting PMOS transistor QPS1 includes a source, a drain, a gate, and a well. The source of the selecting PMOS transistor QPS1 receives an input voltage VIN1. The gate of the selecting PMOS transistor QPS1 receives an input voltage VIN2. The well of the selecting PMOS transistor QPS1 is coupled to the drain of the selecting PMOS transistor QPS1. The selecting PMOS transistor QPS2 includes a source, a drain, a gate, and a well. The source of the selecting PMOS transistor QPS2 receives the input voltage VIN2. The gate of the selecting PMOS transistor QPS2 receives the input voltage VIN1. The well of the selecting PMOS transistor QPS2 is coupled to the drain of the selecting PMOS transistor QPS2. The drains of the selecting PMOS transistors QPS1 and QPS2 are coupled together for outputting an output voltage VOUT.
The high-voltage selecting circuit 100 is utilized for receiving input voltages VIN1 and VIN2, and selecting the higher one of the input voltages VIN1 and VIN2 to generate an output voltage VOUT. For instance, it is assumed that the voltage level of the input voltage VIN1 is fixed and is equal to the voltage level of a supply voltage VDD, which is about 3.3V. When the input voltage VIN2 is about 6˜7.5V (that is, the input voltage VIN2 is higher than the input voltage VIN1), the selecting PMOS transistor QPS1 is turned off and the selecting PMOS transistor QPS2 is turned on. Thus, the voltage level of the voltage on the drain of the selecting PMOS transistor QPS2 is equal to the voltage level of the voltage on the source of the selecting PMOS transistor QPS2. In this way, the voltage level of the output voltage VOUT is equal to that of the input voltage VIN2, which means the high-voltage selecting circuit 100 selects the higher input voltage VIN2 (6˜7.5V) as the output voltage VOUT. When the input voltage VIN2 is about 0V (that is, the input voltage VIN1 is higher than the input voltage VIN2), the selecting PMOS transistor QPS2 is turned off and the selecting PMOS transistor QPS1 is turned on. In this way, the voltage level of the voltage on the drain of the selecting PMOS transistor QPS1 is equal to the voltage level of the voltage on the source of the selecting PMOS transistor QPS1. Therefore, the voltage level of the output voltage VOUT is equal to that of the input voltage VIN1, which means the high-voltage selecting circuit 100 selects the higher input voltage VIN1 (3.3V) as the output voltage VOUT.
However, when the input voltage VIN2 is 3.3V (that is, the voltage level of the input voltage VIN2 is equal to that of the input voltage VIN1, as shown in FIG. 2), both the selecting PMOS transistors QPS1 and QPS2 are turned off. Meanwhile, the parasitic diode DSP1 of the selecting PMOS transistor QPS1 and the parasitic diode DSP2 of the selecting PMOS transistor QPS2 are turned on, so that the voltage level of the output voltage VOUT is equal to that of the input voltage VIN1 (or VIN2) deducting the forward voltage VFW1 (or VFW2) of the parasitic diodes DSP1 (DSP2). For instance, when the forward voltages VFW1 and VFW2 are 0.7V, the output voltage VOUT is 2.6V. However, since both the input voltages VIN1 and VIN2 are 3.3V, the output voltage VOUT should be 3.3V according to the requirement. In other words, the conventional high-voltage selecting circuit 100 generates the output voltage VOUT with a voltage drop.
More particularly, when the voltage level of the input voltage VIN2 is equal to that of the input voltage VIN1, the output voltage VOUT (2.6V) of the conventional high-voltage selecting circuit 100 is not at the required voltage level. If the output voltage VOUT (2.6V) is inputted to an inverter 101 coupled between a supply voltage source VDD (3.3V) and a ground (0V), as shown in FIG. 3, both the PMOS transistor QINVP of the inverter 101 and the NMOS transistor QINVN are turned on. In this way, a large leakage current ILEAK is generated from the supply voltage source VDD to the ground, causing inconvenience to the users.